Abstract
The bandwidth wall between AI accelerator chips has become the primary system-level constraint for training large models. NVLink 4.0 delivers 900 GB/s bidirectional bandwidth between two H100 GPUs, but the physics of copper SerDes at sub-10mm distances limits further scaling without disproportionate power cost. Silicon photonics offers a path to higher bandwidth at lower power per bit for off-chip communication, and the field has moved from research demonstrations to early commercial deployments over the past two years. What is actually shipping, what remains a roadmap commitment, and what the architectural implications are for AI system design are worth examining carefully.
The Physics Driving the Transition
Copper SerDes links at 100 Gbaud+ (as in NVLink 4.0 and PCIe Gen 6) dissipate roughly 1-5 pJ per bit depending on link distance and equalization requirements. At 10+ meter distances, the equalization energy dominates. Silicon photonics (SiPh) modulates data onto optical carriers, which propagate at near-zero attenuation over the distances relevant in a server rack (1-10 meters), with the energy cost dominated by the modulator (electrical-to-optical) and photodetector (optical-to-electrical) conversions rather than distance. Current silicon photonic transceivers in 800G pluggable form factors consume approximately 15-20W for 800 Gb/s aggregate, translating to roughly 20-25 pJ/bit. This is worse than copper at 1 meter but improves linearly with distance - at 5 meters, SiPh is already competitive, and at 10+ meters it is clearly superior. The architectural implication is that SiPh becomes compelling when bandwidth-dense connections need to cross a rack or connect multiple racks, not within a single tray.
What Has Shipped as of Early 2026
The 800G QSFP-DD SR8 and DR8 transceiver ecosystem is mature, with silicon photonics components from Intel’s photonics division, II-VI (now Coherent), and Broadcom’s Avago business shipping in volume to hyperscaler data centers. These are pluggable modules, not co-packaged optics - the electrical-to-optical conversion happens at the module boundary, not adjacent to the die. Co-packaged optics (CPO), where the photonic engine is integrated directly with the switch or accelerator ASIC in the same package, is the higher-bandwidth path that eliminates the high-speed electrical trace between die and module. Ayar Labs demonstrated a CPO integration with TSMC’s InFO packaging platform, achieving approximately 4 Tb/s aggregate bandwidth from a single package. Intel and Ranovus have announced CPO designs targeted at AI switch ASICs. None of these CPO implementations are in volume production as of early 2026 - they are engineering samples or limited pilot deployments - but the timeline for production silicon is 12-18 months for the leading programs.
Architectural Design Space for AI Interconnects
The shift toward SiPh changes the AI cluster topology design space in specific ways. With copper NVLink, the bandwidth budget degrades sharply beyond 2-4 GPU nodes connected by direct cables, driving the fat-tree NVSwitch architectures used in DGX systems. With SiPh at rack scale, flat all-to-all topologies become more viable because the optical links maintain bandwidth over longer distances without passive copper’s cable gauge and bend-radius constraints. Research from Google’s network architecture team (published in proceedings of HotChips 2025) examined rail-optimized topologies for SiPh-connected AI pods and found that reducing the number of switching hops while increasing per-hop bandwidth produces better bisection bandwidth at lower latency than traditional fat-tree topologies for all-reduce collective operations. For system architects planning AI infrastructure deployments in 2026 and 2027, the decision between copper NVLink-class interconnects and SiPh alternatives is primarily a distance and pod-size question, not a bandwidth-per-second question - the two technologies overlap in bandwidth density but diverge sharply in how that bandwidth degrades with distance.