Abstract

DRAM cells leak charge over time and must be periodically refreshed to prevent data loss. As DRAM capacity per rank has grown from gigabytes to tens of gigabytes, the time required to refresh all rows - and the bandwidth and power consumed doing so - has grown proportionally, while the refresh interval mandated by JEDEC standards has remained at 64 milliseconds for standard operation. On a 128 GB DDR5 RDIMM, refresh overhead can consume 5-8 percent of peak memory bandwidth even under the best-case assumptions of the standard. This article examines the microarchitectural techniques being deployed in memory controllers and DRAM devices to reduce that overhead without compromising data integrity.

The Refresh Scaling Problem

A DRAM rank is organized as a matrix of rows, each of which must be activated and precharged - refreshed - within the retention interval. As die density increases through process shrinkage, cell capacitance decreases and leakage increases, requiring either shorter refresh intervals or compensating circuit techniques. JEDEC’s DDR5 specification introduced a 32 millisecond refresh interval option (2x the standard rate) for high-density configurations, doubling refresh overhead for those parts. Simultaneously, the move to per-bank refresh (introduced in DDR4 and retained in DDR5) partially decoupled refresh from normal bank access by allowing individual banks to refresh independently, enabling other banks to service read/write requests during a refresh operation. This architectural change significantly reduced the worst-case latency penalty of a refresh hit on an active bank, but did not reduce the total bandwidth consumed by refresh operations across the rank.

Fine-Grained and Distributed Refresh

The next step beyond per-bank refresh is fine-grained refresh, where instead of refreshing entire rows, the memory controller refreshes smaller sub-arrays or individual cells selectively. LPDDR5X includes a same-bank refresh command that allows a more granular targeting of refresh within a bank. More aggressive proposals in the research literature - including Samsung’s proprietary Adaptive Refresh Technology and Micron’s published work on targeted refresh - use built-in retention testing during manufacturing to identify which rows actually need frequent refresh (weak cells) versus those that can be refreshed less often. The JEDEC standard does not yet mandate retention profiling in standard DIMM modules, but several server memory vendors have begun shipping RDIMMs with factory-written retention maps that the memory controller can exploit if the host firmware supports it.

Temperature-Aware Refresh Scheduling

DRAM retention time is strongly temperature-dependent: cells that need 64 ms refresh at 45 degrees Celsius may only need 16 ms at 85 degrees Celsius and can tolerate 128 ms or more at 25 degrees. Modern server BMCs (Baseboard Management Controllers) expose per-DIMM temperature readings, and several memory controller implementations - including those in recent AMD EPYC and Intel Xeon server platforms - support temperature-aware refresh rate adjustment within the JEDEC-specified extended temperature rate options. EPYC 9004 (Genoa) memory controllers running with DDR5 RDIMMs at server ambient temperatures in the 35-45 degree range have been benchmarked showing 2-3 percent bandwidth improvements from dynamically selecting the 1x refresh rate versus always running the conservative 2x rate required for worst-case thermal conditions. The savings are modest per-DIMM but aggregate meaningfully in memory-bandwidth-bound HPC and database workloads across a fully populated 12-channel system.

Refresh Pausing and Priority Inversion

Even with per-bank refresh, a long burst of consecutive refresh commands on a heavily accessed bank can stall memory requests for many nanoseconds. DDR5’s Refresh Management (RFM) command scheme attempts to address this by allowing the memory controller to defer refresh obligations up to a bounded limit and then discharge them in controlled bursts during idle periods. The tradeoff is that tracking the refresh debt per bank adds state to the memory controller and requires careful scheduling to prevent the debt from accumulating to the point where a mandatory catch-up burst causes a latency spike worse than distributed periodic refreshes would have. Memory controller IP from Synopsys (DesignWare DDR5 PHY) and Cadence now includes RFM-aware schedulers that attempt to discharge refresh debt during inter-burst gaps in naturally occurring request traffic, keeping observed worst-case latency within 10-15 percent of a system without deferred refresh.

Outlook

The most promising long-term direction is in-DRAM ECC combined with targeted refresh, where error-correcting codes within the DRAM die detect cells approaching the reliability threshold and trigger selective refresh before data is lost. SK Hynix’s HBM3E specification includes per-die ECC as a mandatory feature, and similar capabilities are under discussion for future LPDDR and DDR standards. If in-DRAM ECC becomes standard, it creates the architectural basis for substantially extending refresh intervals for the majority of cells while using targeted refresh only for confirmed weak rows - potentially cutting total refresh overhead by half compared to today’s uniform-interval schemes.