Abstract

As chiplet-based designs move from side-by-side 2.5D arrangements to true 3D stacking with die-to-die bonding pitches below 10 micrometers, the power delivery network (PDN) becomes a first-class architectural constraint rather than a packaging afterthought. Current densities in stacked logic dice can exceed 100 mA per square millimeter at advanced nodes, and the thinned silicon in face-to-face bonds eliminates the bulk substrate that traditionally helped spread current. This article examines the PDN challenges unique to 3D-stacked chiplet assemblies and surveys the microarchitectural and packaging techniques being deployed to address them.

The Impedance Problem in Vertical Stacks

A conventional planar PDN distributes power through package traces, C4 bumps, and on-die power grids in a mostly horizontal plane. Stacking adds vertical current paths through micro-bumps or hybrid bonds, each of which introduces inductance proportional to its height. Even a 5-micrometer copper pillar contributes tens of picohenries per bond, which sounds negligible until thousands of switching transistors create simultaneous demand transients in the hundreds of amperes-per-nanosecond range. The result is resonant voltage droops that can exceed 10 percent of the nominal supply, triggering frequency throttling or, in worst cases, timing violations. Intel’s Foveros and TSMC’s SoIC-X stacks both address this by maximizing bond density - more bonds per unit area mean lower per-bond current and aggregate inductance - but the routing complexity grows accordingly.

Decoupling Strategies Across the Stack

The standard response to PDN resonance is decoupling capacitance placed as close as possible to the switching load. In a 3D stack, this creates an opportunity: a base die can be designed primarily as a power delivery and decoupling layer, populated with deep-trench capacitors (DTCs) or metal-insulator-metal (MIM) stacks rather than logic. TSMC’s N3-generation SoIC test vehicles have demonstrated embedded DTCs with capacitance densities above 300 nanofarads per square millimeter, sufficient to suppress mid-frequency droop in overlying compute tiles. The architectural implication is that die partitioning decisions now carry a PDN co-optimization requirement - a compute chiplet’s floorplan must align its power-hungry blocks (execution clusters, SRAM arrays) with the high-capacitance zones of the base die directly beneath them.

Microarchitectural Power Shaping

Packaging solutions alone cannot tame the fastest transients, which originate in the microarchitecture itself. Researchers at ETH Zurich and several industrial labs have demonstrated that coordinating issue slot activity across a wide-issue core can reduce peak current draw by 15-20 percent with under one percent IPC penalty. The technique, variously called current-aware instruction scheduling or PDN-aware dispatch, models PDN impedance as a constraint in the instruction window and throttles back instruction issue momentarily when accumulated switching is projected to exceed a threshold. This requires on-die current sensors - structures already present in some server parts for power management - to close the feedback loop at nanosecond timescales. ARM’s Cortex-X series and AMD’s Zen 4 both include coarse-grained current sensing; finer-grained per-cluster sensing is an active research direction for Zen 5 and successor Cortex designs.

Thermal Coupling and Its PDN Consequences

3D stacking concentrates heat in a smaller volume, which raises die temperatures and increases metal resistivity in the power grid - a feedback loop that worsens voltage droop under sustained load. Thermal-aware PDN simulation tools such as Cadence Voltus-Fi and Ansys RedHawk-SC have added coupled electrothermal solvers specifically to capture this interaction. The practical design implication is that sign-off margins for stacked designs must account for the resistance increase at thermal steady state, not just the ambient-temperature IR drop. Some design teams are adding additional redundant power stripes in thermally hot regions as a margin hedge, accepting the routing overhead to avoid late-stage respins.

Outlook

Power delivery will remain a gating constraint for 3D chiplet scaling through at least 2027, when advanced packaging generations with sub-1-micrometer hybrid bonding pitches are projected to offer enough bond density to substantially reduce per-bond inductance. Until then, the most productive path combines high-density decoupling in base dies, PDN-aware microarchitectural scheduling, and electrothermal co-simulation at sign-off. Teams that treat PDN as an architecture-level concern from the first floorplan will avoid the costly late-stage metal re-spins that have delayed several recent high-profile chiplet products.